DSI TX & RX CONTROLLER
The MIPI display serial interface (DSI) is an interface between a display or other data interface and a host processor base-band application engine.
This interface is defined by MIPI alliance, which defines a series of modules in a MIPI compliant product.
Our MIPI DSI receiver is used in mobile and high–speed serial applications as a controller for receiving video, command or user data transmitted using MIPI DSI transmitter over MIPI lines. It is sent to the next higher level for subsequent processing. The MIPI DSI receiver along with the MIPI DSI transmitter and MIPI DPHY provides a complete solution for MIPI DSI communication.
- Compliant with MIPI DSI-2 standard v0.8.x, MIPI D-PHY standard v1.x, MIPI D-PHY standard V2.x and MIPI C-PHY V1.x
- Up to 3 Gsps per trio using C-PHY. 17Gbps in 3 trios.
- Up to 2.5 Gbps per data lane of D-PHY (V2.0). 10Gbps in 4 lanes
- Programmable 1, 2, 3 (C-PHY) or 4 (D-PHY) data lane configuration
- Forward and reverse communication
- Configurable virtual channel up to 4
- Operate in continuous and non-continuous clock modes
- Command and video mode are supported
- Burst and non-burst modes are supported
- Pulse and event modes supported
- Color modes: 16, 18, 24 and 36 bpp
- Display stream compression (DSC) supported
- Data lane count
- Color modes
- Pixel interface width
- Application interface – Pixel, AXI
- Command FIFO depth
- Data lane count
- Highly modular and configurable design
- Layered architecture
- Active low async reset
- Clearly de-marked clock domains
- Extensive clock gating support
- Configurable RTL code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- Documentation (Design, verification, and synthesis guides)