Very Large Scale Integration (VLSI)
The semiconductor industry is in the midst of a major disruption, with reports forecasting the economic infeasibility of miniaturizing traditional transistors in microprocessors post-2021. In light of this seismic shift, enterprises are collaborating with equipment and materials suppliers to optimize operations and provide greater end-value to customers. Additionally, manufacturers are formulating design strategies that incorporate a vertical chip geometry, while adopting shrinking technologies for current market requirements. This will mean streamlining production—capable of delivering more derivatives from a single product line, ensuring IP customization and SoC integration, among others. As a result, enterprises need to partner with very-large-scale integration (VLSI) service providers to meet demanding timelines, while simultaneously ensuring quality and conducting R&D for future technology manufacturing needs.
- Turkey SoC development
- Pre-Si Verification
- RTL design
- Post-Si validation
- Physical Design
- Design for testing
- Static timing analysis
- Over 15 years of experience with multi-million gate designs
- More than 70 successful tape-outs of up to 28nm, including low-power designs
- Extensive experience with the mixed tool set flows and in-house repositories of EDA tools licenses
- Strategic partnerships to fortify fixture manufacturing and enable joint GTM
Complex embedded software algorithms can run up to 100 million lines of code, all written manually. We discuss 5 trends that suggest a leaner, model-based approach could become ‘the new normal’.
Complete physical design & verification of image processing SoC. Executed the chip & SoC plan using low power methods. 5 Mn gates with 400+ macros, & 40 processing algorithms.
DFT for Power PC Chip – integrated block level scan chain with top level and optimized MBIST and functional signals to reduce congestion. 16 chains with a maximum of 12500 flip flops.
FPGA prototyping for a consumer device & gaming application. Developed clocking & reset scheme, leveraged in-house IP address & board design to reduce integration time.